Layout Extraction and Veri cation Methodology for CMOS I/O Circuits

This paper presents a layout extraction and veri cation methodology which targets reliability-driven I/O design for CMOS VLSI chip, speci cally to guard against electrostatic discharge (ESD) stress and latchup. We propose a new device extraction approach to identify devices commonly used in CMOS I/O circuits including MOS transistors, eld transistors, di usion and well resistors, diodes and silicon controlled recti ers (SCRs), etc. Unlike other extractors, our extractor identi es circuit-level netlist based on the speci ed ESD stress condition. In addition, novel techniques are proposed for the identi cation of parasitic bipolar junction transistors (BJTs).